Field of the Invention
The invention relates in general to a solid state disk (SSD), and more particularly to a method for establishing a translation layer to manage a logical to physical (L2P) table when the SSD is activated.
Description of the Related Art
Solid state disk (SSD) is a storage device composed of NAND flash memory arrays. The flash memory is subjected to the erase times, and data is scattered to store in the flash memory arrays. The flash translation layer (FTL) is used to manage the correspondence relationship between the logical address of data and the physical address in which data is actually stored in the flash memory.
Referring to FIG. 1, a functional block diagram of an electronic device storage system 1 in the prior art is shown. The host 2 of the electronic device storage system 1, such as a computer, a mobile phone, includes a central processing unit (CPU) 3, which sends the logical address of the accessed data to the SSD 5 connected to the transmission interface 4. The SSD 5 includes a controller 6. The controller 6, in conjunction with a buffer memory 7, receives the logical address of the accessed data from the host 2, accesses data from the physical address of the flash memory array 8 corresponding to the logical address of the accessed data, and sends the accessed data to the DRAM 9 for the host 2 to use.
In order to manage the relationship between the logical address of data and the physical address in which data is actually stored in the flash memory array 8, a flash translation layer (FTL) is established for the storage and management of a logical to physical table (L2P) table. When the SSD 5 is activated, management data of each data block is read from the flash memory array 8 to form an L2P table storing the correspondence relationship between the logical address of data and the physical address of the accessed data. When the SSD 5 is initialized, the firmware stored in the flash memory array 8 of the SSD 5 already pre-determines that the FTL is established in the buffer memory 7 or the flash memory array 8. Since the access speed of the dynamic random access memory (DRAM) is 10 times faster than that of the flash memory, the buffer memory 7 is a DRAM type buffer memory. Thus, in the prior art, the FTL is preferably established in the buffer memory 7 of the SSD 5.
Since the FTL is preferably established in the buffer memory 7 of the SSD 5 in the prior art, the FTL cannot be established once the buffer memory 7 is broken or partially damaged. If the establishing position of FTL cannot be changed, the SSD 5 can no longer use the FTL to manage the L2P table of the accessed data. To the worse, the SSD 5 will fail. If the FTL of the SSD 5 is established in the flash memory array having a slower access speed, the establishing position of the FTL cannot be adjusted according to the state of the electronic device storage system, and the access speed of the SSD cannot be increased. Therefore, the SSD still has any problems to resolve when it comes to the establishment method of the translation layer.